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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:12:33 03/18/2011 
-- Design Name: 
-- Module Name:    pc - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pc is
    Port ( clk      : in  STD_LOGIC;
           pc_reset : in  STD_LOGIC;
           pc_en    : in  STD_LOGIC;
           pc_in    : in  STD_LOGIC_VECTOR (9 downto 0);
           pc_out   : out STD_LOGIC_VECTOR (9 downto 0));
end pc;

architecture RTL of pc is
	begin
	process (clk, pc_reset) --reloj y reset	
   variable pc_val : STD_LOGIC_VECTOR (9 downto 0); --contenido del PC	
	
		begin	
		if rising_edge (clk) then
			if pc_reset = '0' then
				pc_val := (others => '0'); -- rellena con 0 el std_logic_vector
			if pc_en = '1' then
				pc_val := pc_in;				
			end if;
			end if;
		end if;
		pc_out <= pc_val;
	end process;
end RTL;



























